Skill Guide

Hardware profiling and optimization - GPU memory management, CUDA tuning, CPU SIMD, Apple Metal, NPU acceleration

The systematic profiling, analysis, and optimization of computational kernels and data movement across heterogeneous hardware accelerators (GPU, CPU SIMD, NPU) to maximize throughput, minimize latency, and achieve optimal performance-per-watt.

This skill directly reduces infrastructure costs by enabling more work per dollar on cloud or edge hardware. It is critical for deploying latency-sensitive AI inference, real-time graphics, and HPC workloads at scale, providing a significant competitive advantage.

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How to Learn Hardware profiling and optimization - GPU memory management, CUDA tuning, CPU SIMD, Apple Metal, NPU acceleration

1. Understand hardware hierarchy: CPU cores (registers, L1/L2 cache, SIMD units), GPU architecture (streaming multiprocessors, warp/wavefront scheduling, memory hierarchy). 2. Master profiling tool output: Learn to read flame graphs, roofline models, and memory transfer timelines. 3. Write basic, correct CUDA kernels or Metal compute shaders.

1. Move from theoretical occupancy to measured SM utilization using `nsight-compute`. 2. Profile and eliminate memory bottlenecks: coalescing, bank conflicts, shared memory tiling. 3. Implement CPU SIMD intrinsics (`_mm256_fmadd_ps`) and measure cache miss rates via `perf stat`. Avoid premature optimization without profiling data.

1. Architect data pipelines that maximize GPU-CPU-NPU concurrency (e.g., using CUDA Graphs, Metal Indirect Command Buffers). 2. Develop custom memory allocators and pool strategies for specific workload patterns. 3. Mentor teams on establishing a performance culture with CI/CD-integrated benchmarks and regression detection.

Practice Projects

Beginner

Project

GPU Memory Bandwidth Optimization

Scenario

A naive matrix transpose kernel is running 3x slower than the memory bandwidth limit suggests it should.

How to Execute

1. Profile the kernel with `ncu` (Nsight Compute) to identify high global memory load/store inefficiencies. 2. Implement a tiled transpose using shared memory to coalesce global memory accesses. 3. Profile again to measure achieved bandwidth and compare to the hardware's theoretical peak. 4. Experiment with different tile sizes to find the optimal configuration.

Intermediate

Project

Heterogeneous Pipeline for Video Inference

Scenario

Design a system to run object detection on a 4K video stream with <50ms latency on a system with an NVIDIA GPU, a modern x86 CPU, and an NPU.

How to Execute

1. Profile the full pipeline: decode (CPU), pre-process (CPU SIMD), inference (GPU/NPU), post-process (CPU). 2. Use `nsight-systems` to identify serialization and data transfer stalls. 3. Implement concurrent pipelines: decode frame N+1 while inferring on frame N. 4. Offload post-processing (NMS) to CPU SIMD or a separate NPU subgraph to hide latency.

Advanced

Project

Custom Allocator for Dynamic Graph Neural Networks

Scenario

A GNN training framework suffers from OOM errors and severe memory fragmentation due to variable-sized graph tensors.

How to Execute

1. Analyze memory allocation patterns over time using custom allocator hooks or `torch.cuda.memory_stats()`. 2. Design a pooled, slab-based memory allocator for fixed-size feature blocks and a separate arena for variable-length indices. 3. Implement the allocator to be thread-safe and CUDA-graph-capture compatible. 4. Benchmark training throughput and memory high-water mark against the default PyTorch allocator.

Tools & Frameworks

Profiling & Analysis

NVIDIA Nsight Systems (nsight-sys)NVIDIA Nsight Compute (ncu)Intel VTune ProfilerAMD ROCm rocprofApple Instruments (Metal System Trace)Linux perf, bpftrace

Used for timeline analysis, kernel-level metrics (stalls, occupancy, memory throughput), and system-wide bottleneck identification. The primary tool for moving from guesswork to data-driven optimization.

Compute & Optimization Libraries

CUDA Toolkit (cuBLAS, cuDNN, CUTLASS)OpenMP/SIMD pragmasARM NEON/Apple AMX IntrinsicsoneAPI (oneMKL, oneDNN)Metal Performance Shaders (MPS)

Highly optimized, vendor-provided implementations of common operations (GEMM, conv). Learning to correctly use and configure them is the first step to achieving near-peak performance.

Memory & Concurrency Frameworks

CUDA GraphsMetal Indirect Command BuffersUnified Memory (CUDA/Apple Silicon)Custom C++ Allocators (e.g., using std::pmr)MPI + CUDA-aware libraries

For managing complex execution graphs, data transfers, and memory lifecycles to hide latency and maximize hardware utilization across multiple devices or processes.

Interview Questions

Answer Strategy

The candidate must demonstrate a systematic, tool-driven approach. They should mention: 1) Checking memory transaction efficiency (coalescing), 2) Analyzing shared memory usage and bank conflicts, 3) Considering algorithmic changes (tiling, recomputation) to increase arithmetic intensity, 4) Verifying they aren't hitting a memory bandwidth limit. Sample Answer: 'I would first inspect the `Global Memory Load/Store Efficiency` metric. If below 100%, I'd restructure memory access patterns. Next, I'd check for shared memory bank conflicts via the `Shared Memory Bank Conflict` metric. If those are optimal, I'd profile the kernel's algorithmic intensity-perhaps implementing loop tiling to reuse data from shared memory, thereby increasing FLOPs per byte loaded from global memory.'

Answer Strategy

This tests understanding of trade-offs beyond peak FLOPs. The answer should highlight latency, power, data movement cost, and hardware availability. Sample Answer: 'For a sub-2ms latency requirement on a single-image classification task in an edge device without a discrete GPU, I used AVX2. The key factors were: 1) Eliminating PCIe/host-device memory copy latency, 2) Lower power consumption, 3) Avoiding GPU kernel launch overhead for a very small workload. I optimized the model with quantization (INT8) and used Intel's OpenVINO to leverage VNNI instructions for maximum throughput.'